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6.823 Computer System Architecture (MIT) 6.823 Computer System Architecture (MIT)

Description

6.823 is a study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics may include: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; VLIW machines; vector supercomputers; multithreaded architectures; symmetric multiprocessors; and parallel computers. 6.823 is a study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics may include: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; VLIW machines; vector supercomputers; multithreaded architectures; symmetric multiprocessors; and parallel computers.

Subjects

computer architecture | | computer architecture | | computer system architecture | | computer system architecture | | hardware | | hardware | | hardware design | | hardware design | | software | | software | | software design | | software design | | instruction set design | | instruction set design | | processor micro-architecture | | processor micro-architecture | | pipelining | | pipelining | | cache memory | | cache memory | | irtual memory | | irtual memory | | I/O | | I/O | | input/output | | input/output | | interrupts | | interrupts | | superscalar architectures | | superscalar architectures | | VLIW machines | | VLIW machines | | vector supercomputers | | vector supercomputers | | multithreaded architectures | | multithreaded architectures | | symmetric multiprocessors | | symmetric multiprocessors | | parallel computers | parallel computers | computer architecture | computer architecture | computer system architecture | computer system architecture | hardware | hardware | hardware design | hardware design | software | software | software design | software design | instruction set design | instruction set design | processor micro-architecture | processor micro-architecture | pipelining | pipelining | cache memory | cache memory | virtual memory | virtual memory | I/O | I/O | input/output | input/output | interrupts | interrupts | superscalar architectures | superscalar architectures | VLIW machines | VLIW machines | vector supercomputers | vector supercomputers | multithreaded architectures | multithreaded architectures | symmetric multiprocessors | symmetric multiprocessors

License

Content within individual OCW courses is (c) by the individual authors unless otherwise noted. MIT OpenCourseWare materials are licensed by the Massachusetts Institute of Technology under a Creative Commons License (Attribution-NonCommercial-ShareAlike). For further information see http://ocw.mit.edu/terms/index.htm

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6.823 Computer System Architecture (MIT) 6.823 Computer System Architecture (MIT)

Description

6.823 is a course in the department's "Computer Systems and Architecture" concentration. 6.823 is a study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics may include: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; VLIW machines; vector supercomputers; multithreaded architectures; symmetric multiprocessors; and parallel computers. 6.823 is a course in the department's "Computer Systems and Architecture" concentration. 6.823 is a study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics may include: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; VLIW machines; vector supercomputers; multithreaded architectures; symmetric multiprocessors; and parallel computers.

Subjects

computer architecture | computer architecture | computer system architecture | computer system architecture | hardware | hardware | hardware design | hardware design | software | software | software design | software design | instruction set design | instruction set design | processor micro-architecture | processor micro-architecture | pipelining | pipelining | cache memory | cache memory | virtual memory | virtual memory | I/O | I/O | input/output | input/output | interrupts | interrupts | superscalar architectures | superscalar architectures | VLIW machines | VLIW machines | vector supercomputers | vector supercomputers | multithreaded architectures | multithreaded architectures | symmetric multiprocessors | symmetric multiprocessors | parallel computers | parallel computers | computer system | computer system

License

Content within individual OCW courses is (c) by the individual authors unless otherwise noted. MIT OpenCourseWare materials are licensed by the Massachusetts Institute of Technology under a Creative Commons License (Attribution-NonCommercial-ShareAlike). For further information see http://ocw.mit.edu/terms/index.htm

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6.823 Computer System Architecture (MIT)

Description

6.823 is a study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics may include: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; VLIW machines; vector supercomputers; multithreaded architectures; symmetric multiprocessors; and parallel computers.

Subjects

computer architecture | | computer system architecture | | hardware | | hardware design | | software | | software design | | instruction set design | | processor micro-architecture | | pipelining | | cache memory | | irtual memory | | I/O | | input/output | | interrupts | | superscalar architectures | | VLIW machines | | vector supercomputers | | multithreaded architectures | | symmetric multiprocessors | | parallel computers | computer architecture | computer system architecture | hardware | hardware design | software | software design | instruction set design | processor micro-architecture | pipelining | cache memory | virtual memory | I/O | input/output | interrupts | superscalar architectures | VLIW machines | vector supercomputers | multithreaded architectures | symmetric multiprocessors

License

Content within individual OCW courses is (c) by the individual authors unless otherwise noted. MIT OpenCourseWare materials are licensed by the Massachusetts Institute of Technology under a Creative Commons License (Attribution-NonCommercial-ShareAlike). For further information see https://ocw.mit.edu/terms/index.htm

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6.823 Computer System Architecture (MIT)

Description

6.823 is a course in the department's "Computer Systems and Architecture" concentration. 6.823 is a study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics may include: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; VLIW machines; vector supercomputers; multithreaded architectures; symmetric multiprocessors; and parallel computers.

Subjects

computer architecture | computer system architecture | hardware | hardware design | software | software design | instruction set design | processor micro-architecture | pipelining | cache memory | virtual memory | I/O | input/output | interrupts | superscalar architectures | VLIW machines | vector supercomputers | multithreaded architectures | symmetric multiprocessors | parallel computers | computer system

License

Content within individual OCW courses is (c) by the individual authors unless otherwise noted. MIT OpenCourseWare materials are licensed by the Massachusetts Institute of Technology under a Creative Commons License (Attribution-NonCommercial-ShareAlike). For further information see https://ocw.mit.edu/terms/index.htm

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6.823 Computer System Architecture (MIT)

Description

6.823 is a course in the department's "Computer Systems and Architecture" concentration. 6.823 is a study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics may include: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; VLIW machines; vector supercomputers; multithreaded architectures; symmetric multiprocessors; and parallel computers.

Subjects

computer architecture | computer system architecture | hardware | hardware design | software | software design | instruction set design | processor micro-architecture | pipelining | cache memory | virtual memory | I/O | input/output | interrupts | superscalar architectures | VLIW machines | vector supercomputers | multithreaded architectures | symmetric multiprocessors | parallel computers | computer system

License

Content within individual OCW courses is (c) by the individual authors unless otherwise noted. MIT OpenCourseWare materials are licensed by the Massachusetts Institute of Technology under a Creative Commons License (Attribution-NonCommercial-ShareAlike). For further information see https://ocw.mit.edu/terms/index.htm

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https://ocw.mit.edu/rss/all/mit-allcourses.xml

Attribution

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